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TOOL IDB-SWE-012
I²C / SPI speed budget

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I²C / SPI speed budget

Effective throughput vs target sample rate. Accounts for overhead, ACK bits, start/stop, register selection.

Transaction layout I²C 400 kHz
SCL / SDA S start ADDR · R/W 8 bits A ack REG ADDR 8 bits A DATA × N + ACK N × 9 bits P stop tx — µs BUS UTILISATION (1 s) — % 50% 80% —
Engineering notes

I²C overhead

  • 9 bits per byte (8 data + 1 ACK).
  • Start + addr + register-select + restart + repeat addr ≈ ~30 bits per transaction.
  • Quoted bus speed is the SCL period — actual data rate is <80% of that.
  • Clock stretching: a slave may hold SCL low after any byte, inflating real transaction time.

SPI

  • No ACK bits — overhead is just CS toggle (~1 byte time).
  • Full-duplex; useful throughput = bytes per transfer × frequency / 8.
  • For DMA-based SPI, CPU is free during transfer — see if your peripheral chains.

Result

Live