Services / Electronics manufacturing
Ideambox specifies the board, coordinates the firmware, and takes it into production with an electronics engineering partner under a standing agreement. PCB fabrication and PCBA assembly go through production partners we have worked with for over 15 years, against a package we write: stack-up, stencil, test fixture, BOM, approved vendor list, and a manufacturing test mode the line actually uses.
Ideambox executes production. It does not own the lines. PCB fabrication and PCBA assembly run through production partners we have worked with for over 15 years — injection moulding and PCB manufacturing among others — which means the board and the enclosure it lives in come out of one programme, on one revision, against one set of drawings. Nobody is handed a contact and left to negotiate their own tolerances.
Schematic, layout and firmware stay with the team that owns the product, backed by an electronics engineering partner under a standing agreement. That is capacity without a subcontract chain: the engineer who set the stack-up answers the fab's DFM query, and the engineer who wrote the manufacturing test mode is the one who answers when a station starts failing units.
Gerbers verified in a CAM viewer, a drill file that matches the design, pick-and-place with X, Y and rotation per component, the BOM in the assembler's own format, an assembly drawing carrying the critical mechanical features, the stencil file, a test-point report for ICT, panelisation (V-score, tabs, mouse-bites), and soldermask and silkscreen artwork. Quotes against that package are comparable. A quote against a zipped CAD file is a guess that becomes a change order.
Taiwan is the engineering hub for PCBA and IP-sensitive electronics: first production in 35–60 days, MOQs from 100–1 000 on electronics, and no Section 301 duty for US importers. Mainland China iterates faster and sits deeper in the component supply chain: first production in 30–45 days, MOQ 500–2 000. A standard 4-layer, 50-component PCBA benchmarks at $3–7 in China and $4–8 in Taiwan. The choice is made per board, against volume and IP exposure, not once for the whole company.
Prototype to production handoff
An EVT board that behaves on the bench has proved the architecture. It has not proved that a panel of them can be fabricated, populated, tested and shipped. The gap between the two is a fixed list of releases, each with an owner and a date, closed before the fab is booked rather than discovered at first article.
Four layers — signal, ground, power, signal — is the working default for anything carrying a fast bus: a solid ground plane directly under the top signal layer, and a stack kept symmetric about the centre so the board does not warp in reflow. We give the fab the impedance targets and the layers they apply to — 50 Ω single-ended, 90 Ω differential for USB, 100 Ω for Ethernet and LVDS — and let them set trace width and spacing for their actual laminate. Laminate, copper weight (1 oz default, 2 oz where current demands it), finish (HASL for cost, ENIG for fine-pitch flatness), minimum trace and space, and drill aspect ratio go on the fab notes, not into an email thread.
Assembly DFM is a separate review from fab DFM, and it is the one that gets skipped. Half a millimetre between SMD parts, a millimetre wherever a rework iron has to reach. Three global fiducials, local fiducials on anything 0402 and finer and on every BGA. Test pads 1.0 mm across on a 2.54 mm grid, at least one per net, so the ICT fixture can actually reach what the test plan claims to cover. Keep-outs of 1 mm at connectors, 2 mm at antennas, 3 mm around shielding cans. Then the stencil — a $30–150 consumable that decides whether the first panel comes off the line bridged. Its apertures are tuned to the pads, not left at the default.
MTM is the firmware mode the production line uses to verify every unit, and it is the production-readiness feature most often added too late to be useful. We write the thirteen-stage sequence first: chip ID, power rails measured to ±5 %, LEDs, every button registered inside 30 s, I/O continuity, UART / SPI / I²C loopback, an RF beacon with an RSSI window, a sensor sample under known conditions, then per-unit calibration, serial, MAC and region written once, and lockout. Each stage emits structured pass/fail to the fixture log, and the full pass runs in under 30 seconds a board rather than five minutes. Shipping firmware has MTM disabled and recovery gated behind JTAG. Production, manufacturing, debug and engineering are separate signed builds, not one image with a flag.
EMC is mostly loop area. A continuous reference plane under every fast trace with no split to detour around, 100 nF on every IC power pin, a filter and a common-mode choke at every cable entry, slower edges wherever speed buys nothing, 360° shield bonds instead of pigtails, and a TVS with series impedance on every exposed port — clamped at the connector, with a short path to chassis rather than through the board. ESD is designed to IEC 61000-4-2 level 4: ±8 kV contact, ±15 kV air. A pre-compliance scan in a 3-metre semi-anechoic chamber surfaces harmonics 6–10 dB before the formal run against EN 55032 and FCC Part 15, at €1.5–3k rather than €8–15k for a full retest after the boards are built.
Every line carries the seventeen fields that let it be quoted, ordered, received and traced: manufacturer and MPN, distributor code, lifecycle state, current lead time, MOQ, a second-source MPN, and a critical flag on anything that stops the line when it is missing. Lifecycle is checked rather than assumed — NRND typically gives 6–24 months of warning, a last-time-buy 90–180 days. A-parts are roughly 10 % of the lines and 70 % of the cost, so they get a monthly check and a mandatory second source. Standard leads run 4–12 weeks and stretch to 16–52 in an allocation event, which is the variance safety stock is sized against.
A second source is qualified before it is needed: datasheet deltas documented, drop-in versus hardware-variant decided, samples verified in the actual product, and a 100-unit prove-out before a third source goes anywhere near production. The approved vendor list records all of it, with conditions where they apply. Purchasing stays with authorised distributors and a certificate of conformance carrying date code, lot and fab ID. Independent channels are for EoL parts only, and then verified by X-ray, decap or functional test at roughly $500–2 000 a lot. A price 30 % under market is the first counterfeit signal, not a negotiating win.
Scope of the build
Rigid FR-4 from two layers up, with a 4-layer impedance-controlled stack as the usual starting point. Laminate, copper weight, finish, class and the impedance table are released with the Gerbers and the drill file, so the fab quotes a specification rather than an interpretation.
SMT and through-hole against a released stencil, pick-and-place file and assembly drawing. First article verified before the panel count goes up, manufacturing test mode run on every unit, and the test fixture validated to catch the same defects batch after batch before volume is authorised.
The same programme reaches the moulded parts the board sits in, through injection moulding partners of the same fifteen-year standing. PCB outline, mounting, connector access, antenna keepout and assembly sequence get settled once, instead of being renegotiated between two suppliers who have never spoken.
The partner model
The build sits with partners: injection moulding and PCB manufacturing partners of more than fifteen years, an electronics engineering partner under a standing agreement, and a Taiwan sourcing partner we work with regularly. What does not move is engineering ownership. The specification the partner builds to is ours to write, and the review that says it was built to specification is ours to run.
Quality plan and ramp
One production unit is signed and dated by both sides and kept in two places: one on the production floor, one with you. Everything after that is measured against that unit rather than against a render or a memory of the EVT build. The inspection plan is written against it — AQL levels per ISO 2859-1 level II, critical at 0 %, major at 2.5 %, minor at 4.0 %, with a defect catalogue made of photographs rather than adjectives. A lot of 3 201–10 000 units draws a 200-piece sample: ten major defects accept, eleven reject. Pre-shipment inspection runs against that plan before the batch leaves, and the report answers your criteria, not the line's.
Related reference documents
Schematic hygiene, stack-up selection, decoupling, signal integrity, EMC layout, and the DRC and DFM rules set before the board is fabricated.
IDB-STK-046Common stacks, microstrip versus stripline, 50 / 90 / 100 Ω targets, return paths, and what belongs on the fab notes.
IDB-FWA-020Boot and OTA architecture, the thirteen-stage Manufacturing Test Mode sequence, lockout, and the EU CRA / UK PSTI baseline.
IDB-ESD-049Grounding and return paths, filtering and decoupling, layout, TVS on exposed I/O, cables and shielding — the checklist before the lab.
IDB-BOM-005The seventeen-column BOM, lifecycle states, second-source qualification, MOQ economics, counterfeit signals. Includes XLSX BOM template.
IDB-RMP-021Pilot-to-MP gate criteria, yield ramp targets, fixture validation, operator training, and capacity planning for the first weeks of volume.
There is no standard package and no rate card, because the shape of the work changes with the product. What is released, how many suppliers a build needs, whether tooling exists, the first production quantity and the date it has to hit all move the scope, and they move it a long way. Scope and commercial terms are agreed per project, in writing, before anything starts.
Send the drawing package, the BOM if there is one, the quantity and the date. That is enough to come back with what the work involves.
Send the schematic, the BOM and the volume, and we will tell you what has to close before a fab or an assembler can quote it properly.